How to read registered nets from a faster clock than what's writing

Upon host write, a counter is incremented and then on the slave side, we look for changes.

On host:

if rst = '1' then
  write_count <= (others => '1');
elsif rising_edge(clk1) and (we = '1') then
  write_count <= host_count + X"00000001"; -- if it's 32 bit?
end if;

On slave:

if rst = '1' then
  current_count <= (others => '1');
  previous_count <= (others => '1'); -- why are they both at 1? simple, we start as 0 on the host
elsif rising_edge(clk2) then
  current_count <= write_count;
  previous_count <= current_count;
end if;

new_data <= '1' when current_count /= previous_count;
/r/FPGA Thread