Could someone please explain why it is or is not possible to prototype an SoC by daisy chaining a bunch of FPGAs?

An FPGA is a digital device, so you can't build an analog/RF/mixed signal SoC with just FPGAs

Xilinx would beg to differ :)

You are just limited by bus speed between the FPGAs

Bus speed can be ... impressive. I worked on a project which had a few of the most expensive FPGAs on the planet linked up, each with their own high-end PC to host/monitor them via PCIe. The interconnect between the FPGAs was over a 100Gbit/sec multiple-fibre set-of-links-per node using transceivers and the AXI bus was shared across the interconnect - IIRC (this was a few years back) it was using Aurora as the underlying tech to serialise data from the AXI bus in and out of the chips. There was an entire wall full of these PC/monitor combinations, it was quite something to see at the time.

The product was ultimately converted into a rather impressive SOC, but all the prototyping was done with these FPGAs linked up together.

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