I am a UVVM user and I don't understand the problems you are seeing with UVVM. Their BFMs can be used right out of the box, and I have even used them with some old testbenches where we added a new interface for Axi stream. I just looked at the bfm documentation they call quick reference and used the example there. It worked good in my old test and also in our new one.

So how anyone (the other answer here) can say that UVVM forces you to a specific verbose style is very strange for me. I know they recommend a way to do things with a structured test harness and all that, but i think that is just something they recommend to promote a good methodology and you don't need to follow that at all but only make it your own personal style or even modify some really old testbenches with no style at all. You write the code the way you like it and it works to use only the UVVM commands i need or the bmfs I need.

UVVM has many more BFMs than anyone else. Just take a look at github https://github.com/UVVM

But see for yourself. I just received an email from Mentor about a new free webinar series on VHDL https://www.mentor.com/products/fpga/series/fpga-vhdl-verification-series and UVVM is presented there. First an introduction to UVVM on May 13th and then on advanced UVVM verification on May 20th. Watch and judge.