-- Module Name: LCD_display - Behavioral -- Project Name: -- Target Devices: -- Tool versions:
-- Revision: -- Revision 0.01 - File Created
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_unsigned.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values --use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating -- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all;
entity LCD_display is Port ( LCD : out STD_LOGIC_VECTOR (7 downto 0); RS : out STD_LOGIC; RW : out STD_LOGIC; En : out STD_LOGIC; Clear: in STD_LOGIC; Data_in : in STD_LOGIC_VECTOR (7 downto 0); Clk_100MHz : in STD_LOGIC); end LCD_display;
architecture Behavioral of LCD_display is
signal prescaler: STD_LOGIC_VECTOR (25 downto 0);
signal clock_slow:STD_LOGIC;
type state_type is ( S0, S1, S2, S3, S4, S5, S6, S7, S8, S9,
S10, S11, S12, S13, S14, S15, S16, S17, S18, S19,
S20, S21, S22, S23, S24, S25, S26, S27, S28, S29,
S30, S31, S32, S33, S34, S35, S36, S37, S38, S39,
S40, S41, S42, S43, S44, S45, S46, S47, S48, S49,
S50, S51, S52, S53, S54, S55, S56, S57, S58, S59,
S60, S61, S62, S63, S64, S65, S66, S67, S68, S69,
S70, S71, S72, S73, S74, S75, S76, S77, S78, S79,IDLE);
signal current_state: state_type;
begin
divide: process(Clk_100MHz) begin if (Clk_100MHz ' event and Clk_100MHz='1') then prescaler<=prescaler+1; end if; end process divide; clock_slow<=prescaler(21);
P1: process (clock_slow) begin if (clock_slow'event and clock_slow = '1') then case current_state is -------------------Function Set------------------- when S0 => current_state <= S1;
LCD <= "00111000";
EN <= '0';
RW <= '0';
RS <= '0';
when S1 =>
current_state <= S2;
LCD <= "00111000";
En <= '1';
RW <= '0';
RS <= '0';
when S2 =>
current_state <= S3;
LCD <= "00111000";
EN <= '0';
RW <= '0';
RS <= '0';
-------------------Display On-------------------
when S3 =>
current_state <= S4;
LCD <= "00001111";
EN <= '0';
RW <= '0';
RS <= '0';
when S4 =>
current_state <= S5;
LCD <= "00001111";
EN <= '1';
RW <= '0';
RS <= '0';
when S5 =>
current_state <= S6;
LCD <= "00001111";
EN <= '0';
RW <= '0';
RS <= '1';
-------------------Clear Display-------------------
when S6 =>
current_state <= S7;
LCD <= "00000001";
EN <= '0';
RW <= '0';
RS <= '0';
when S7 =>
current_state <= S8;
LCD <= "00000001";
EN <= '1';
RW <= '0';
RS <= '0';
when S8 =>
current_state <= S9;
LCD <= "00000001";
EN <= '0';
RW <= '0';
RS <= '0';
------------------ENTRY Mode---------------------------- when S9=> current_state <= S10;
LCD <= "00000111";
EN <= '0';
RW <= '0';
RS <= '0';
when S10 =>
current_state <= S11;
LCD <= "00000111";
EN <= '1';
RW <= '0';
RS <= '0';
when S11 =>
current_state <= S12;
LCD <= "00000111";
EN <= '0';
RW <= '0';
RS <= '0';
------------------SET CGRAM ADDRESS1----------------------------
when S12=>
current_state <= S13;
LCD <= "01001000";
EN <= '0';
RW <= '0';
RS <= '0';
------------------SEND DATA TO CGRAM1 ---------------------------- when S13=> current_state <= S14;
LCD <= "00000000";
EN <= '0';
EN <= '1';
RW <= '0';
RS <= '1';
------------------SET CGRAM ADDRESS2----------------------------
when S14=>
current_state <= S15;
LCD <= "01001001";
EN <= '0';
RW <= '0';
RS <= '0';
-------------------SEND DATA TO CGRAM2 ----------------------------
when S15=>
current_state <= S16;
LCD <= "00000000";
EN <= '0';
EN <= '1';
RW <= '0';
RS <= '1';
------------------SET CGRAM ADDRESS3----------------------------
when S16=>
current_state <= S17;
LCD <= "01001010";
EN <= '0';
RW <= '0';
RS <= '0';
------------------SEND DATA TO CGRAM3 ---------------------------- when S17=> current_state <= S18;
LCD <= "00000000";
EN <= '0';
EN <= '1';
RW <= '0';
RS <= '1';
------------------SET CGRAM ADDRESS4----------------------------
when S18=>
current_state <= S19;
LCD <= "01001011";
EN <= '0';
RW <= '0';
RS <= '0';
------------------SEND DATA TO CGRAM4 ---------------------------- when S19=> current_state <= S20;
LCD <= "00010001";
EN <= '0';
EN <= '1';
RW <= '0';
RS <= '1';
------------------SET CGRAM ADDRESS5----------------------------
when S20=>
current_state <= S21;
LCD <= "01001100";
EN <= '0';
RW <= '0';
RS <= '0';
------------------SEND DATA TO CGRAM5 ---------------------------- when S21=> current_state <= S22;
LCD <= "00011111";
EN <= '0';
EN <= '1';
RW <= '0';
RS <= '1';
------------------SET CGRAM ADDRESS6----------------------------
when S22=>
current_state <= S23;
LCD <= "01001101";
EN <= '0';
RW <= '0';
RS <= '0';
-----------------SEND DATA TO CGRAM6 ----------------------------
when S23=>
current_state <= S24;
LCD <= "00000000";
EN <= '0';
EN <= '1';
RW <= '0';
RS <= '1';
------------------SET CGRAM ADDRESS7----------------------------
when S24=>
current_state <= S25;
LCD <= "01001110";
EN <= '0';
RW <= '0';
RS <= '0';
------------------SEND DATA TO CGRAM7 ----------------------------
when S25=>
current_state <= S26;
LCD <= "00000100";
EN <= '0';
EN <= '1';
RW <= '0';
RS <= '1';
------------------SET CGRAM ADDRESS8----------------------------
when S26=>
current_state <= S27;
LCD <= "01001111";
EN <= '0';
RW <= '0';
RS <= '0';
------------------SEND DATA TO CGRAM8 ---------------------------- when S27=> current_state <= S28;
LCD <= "00000000";
EN <= '0';
EN <= '1';
RW <= '0';
RS <= '1';
--------------------------READ DATA FROM CGRAM-------------------------------- when S28 => current_state <= S29;
LCD <= "01001000";
EN <= '0';
EN <= '1';
RW <= '1';
RS <= '1';
when S29 =>
current_state <= IDLE;
when IDLE =>
current_state <= IDLE;
when others =>
current_state <= IDLE;
end case;
end if;
end process P1;
end Behavioral;
---------------------This is the code i tried with it but as i mentioned i'm newto VHDL design will you help me with us