This is how you should present your code

```vhdl library IEEE;

use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all;

entity CU is port( I_clk : in STD_LOGIC; I_en : in STD_LOGIC; alu : in STD_LOGIC; rst : in STD_LOGIC; Inst_in : in STD_LOGIC_VECTOR(11 downto 0); Ra, Rb, Rd : inout STD_LOGIC_VECTOR(7 downto 0); data_in : inout STD_LOGIC_VECTOR(15 downto 0) ); end CU;

architecture Behavioral of CU is

-----OPCODE Select for Control Unit--------------------------
constant ADD      : std_logic_vector(2 downto 0) := "000";
constant SUB      : std_logic_vector(2 downto 0) := "001";
constant AND_bit  : std_logic_vector(2 downto 0) := "010";
constant OR_bit   : std_logic_vector(2 downto 0) := "011";
constant CMA      : std_logic_vector(2 downto 0) := "100";
constant XOR_bit  : std_logic_vector(2 downto 0) := "101";
constant Read_op  : std_logic_vector(2 downto 0) := "110";
constant Write_op : std_logic_vector(2 downto 0) := "111";
-------------------------------------------------------------

signal M1        : std_logic_vector(7 downto 0);
signal M2        : std_logic_vector(7 downto 0);
signal opcode    : std_logic_vector(2 downto 0);
signal regselect : std_logic_vector(5 downto 0);
signal PC        : std_logic_vector(3 downto 0) := "0000";

constant Int_add : std_logic_vector(3 downto 0) := "0000";

begin

process(I_clk, I_en, rst, Inst_in, data_in, PC)
begin
    if rising_edge(I_clk) and I_en = '1' then

        --Program Counter--
        if rst = '1' then
            PC <= Int_add;
        else

            M1 <= data_in(7 downto 0);
            M2 <= data_in(15 downto 8);

            Ra <= M1;
            Rb <= M2;

            regselect <= Inst_in(8 downto 3);
            opcode    <= Inst_in(11 downto 9);

            PC <= PC + 1;

        end if;

        ---Register Select for ALU Operations---
        if regselect <= "001001" and alu = '1' then
            ---OPCODE Operations---

            case opcode is
                when ADD      => Rd <= Ra + Rb;
                when SUB      => Rd <= Ra - Rb;
                when AND_bit  => Rd <= Ra and Rb;
                when OR_bit   => Rd <= Ra or Rb;
                when CMA      => Rd <= not Ra;
                when XOR_bit  => Rd <= Ra xor Rb;
                when Read_op  => Rd <= Ra;
                when Write_op => Ra <= Rb;
                when others   => null;
            end case;

        end if;

        if regselect <= "101001" and alu = '1' then
            ---OPCODE Operations---
            case opcode is
                when ADD     => Rd <= Ra + Rb;
                when SUB     => Rd <= Ra - Rb;
                when AND_bit => Rd <= Ra and Rb;
                when OR_bit  => Rd <= Ra or Rb;
                when CMA     => Rd <= not Ra;

                when XOR_bit  => Rd <= Ra xor Rb;
                when Read_op  => Rd <= Ra;
                when Write_op => Ra <= Rb;
                when others => null;
                    Rb <= Rd;
            end case;
        end if;
        if regselect <= "011001" and alu = '1' then
            ---OPCODE Operations---
            case opcode is
                when ADD      => Rd <= Ra + Rb;
                when SUB      => Rd <= Ra - Rb;
                when AND_bit  => Rd <= Ra and Rb;
                when OR_bit   => Rd <= Ra or Rb;
                when CMA      => Rd <= not Ra;
                when XOR_bit  => Rd <= Ra xor Rb;
                when Read_op  => Rd <= Ra;
                when Write_op => Rd <= Rb;
                when others =>
                    null;
                    Ra <= Rd;
            end case;
        end if;
    end if;
end process;

end Behavioral; ```