Is it possible to have a "partial cutout" on a 4-layer PCB?

100% agree. Any supplier that provides EmIB substrates (i.e., silicon in a cavity with some extra secret sauce) can probably make bare cavities as part of their process too. (CYA note: AT&S has public material on their site that mentions they work on Intel EmIB, so it's not an issue to mention acknowledge that they supply that).

The real issue is as /u/kevlarcoated said; Intel gets that because F500 tech money. In my opinion, they're to PCB manufacture as Cadence and MentorGrapics are to design. AT&S and a few other "tier 1" vendors are really good at delivering leading node PCBs, but it's a completely different world in terms of cost compared to the vendors that normally get discussed here.

/r/PrintedCircuitBoard Thread Parent